In U.S. Pat. No. 5,079,451, Gudger et al. describe a programmable logic device (PLD) having global and local buses providing product terms to a plurality of logic cells. The global bus is capable of communicating with all of the logic cells, while each of the local buses is capable of communicating with only some of the logic cells in the device. Global and local product term signals are produced by AND matrices that are structurally integral with the buses. That is, programmable AND matrices appear as a set of programmable interconnections located where product term lines (logic cell inputs) cross bus lines in the global and local buses. The crosspoint matrices formed by the bus lines, logic cell inputs and programmable interconnections are thus a logic element, essentially a set of wide fan-in AND gates, where the bus lines form the gate inputs and the logic cell inputs form the gate outputs. The logic cells, with their OR gates receiving the resulting product term signals on the logic inputs, form a second level of logic producing sum-of-products terms.
Field programmable gate arrays (FPGAs) typically have a topology where logic blocks are arranged in a two-dimensional array consisting of rows and columns of logic blocks and where interconnect resources occupy the space between the rows and columns. These interconnects form a crosspoint switch matrix that acts to route signals from outputs of the blocks to inputs of the blocks. The interconnect matrix is usually constructed so that signals are potentially routable to all of the logic blocks in the device. However, each logic block input is only connected to one bus line in the interconnect structure.
In U.S. Pat. No. 5,208,491, Ebeling et al. describe a FPGA having a checkerboard array of intermeshed forwardly propagating and backwardly propagating routing and logic blocks (FPRLBs and BPRLBs). A plurality of forwardly propagating and back propagating vertical segmented routing channels (FPSRCs and BPSRCs) serve as signal bus lines between adjacent columns of RLBs. Each FPRLB (or BPRLB) receives an input signal from an immediately adjacent FPSRC (or BPSRC) in one vertical channel and transmits an output signal to another immediately adjacent FPSRC (or BPSRC) in the opposite vertical channel. The individual bus lines in the FPSRCs and BPSRCs are segmented into different lengths allowing short, medium and long range communication with the FPRLBs and BPRLBs.
An object of the present invention is to improve the functional flexibility of programmable logic devices (PLDs) by incorporating some of the interconnection features that presently are found only on FPGAs.